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MC-4532DA726EFB-A10 Datasheet(PDF) 8 Page - Elpida Memory |
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MC-4532DA726EFB-A10 Datasheet(HTML) 8 Page - Elpida Memory |
8 / 16 page Data Sheet E0072N10 8 MC-4532DA726 Synchronous Characteristics Parameter Symbol -A 80 -A 10 Unit Note MIN. MAX. MIN. MAX. Clock cycle time /CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) ns /CAS latency = 2 tCK2 10 (100 MHz) 13 (77 MHz) ns Access time from CLK /CAS latency = 3 tAC3 6 6 ns 1 /CAS latency = 2 tAC2 6 7 ns 1 Input clock frequency 50 125 50 100 MHz Input CLK duty cycle 40 60 40 60 % Data-out hold time /CAS latency = 3 tOH3 3 3 ns 1 /CAS latency = 2 tOH2 3 3 ns 1 Data-out low-impedance time tLZ 0 0 ns Data-out high- impedance time /CAS latency = 3 tHZ3 3 6 3 6 ns /CAS latency = 2 tHZ2 3 6 3 7 ns Data-in setup time tDS 2 2 ns Data-in hold time tDH 1 1 ns Address setup time tAS 2 2 ns Address hold time tAH 1 1 ns CKE setup time tCKS 2 2 ns CKE hold time tCKH 1 1 ns CKE setup time (Power down exit) tCKSP 2 2 ns Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - tCMS 2 2 ns DQMB7) setup time Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - tCMH 1 1 ns DQMB7) hold time Note 1. Output load Output Z = 50 Ω 50 pF Remark These specifications are applied to the monolithic device. |
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