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SSFP8N50 Datasheet(PDF) 1 Page - GOOD-ARK Electronics |
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SSFP8N50 Datasheet(HTML) 1 Page - GOOD-ARK Electronics |
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1 / 2 page  SSFP8N50 StarMOS T Power MOSFET ■ Extremely high dv/dt capability ■ Low Gate Charge Qg results in Simple Drive Requirement ■ 100% avalanche tested ■ Gate charge minimized ■ Very low intrinsic capacitances ■ Very good manufacturing repeatability Description StarMOS is a new generation of high voltage N–Channel enhancement mode power MOSFETs. This new technology minimises the JFET effect, increases packing density and reduces the on-resistance. StarMOS also achieves faster switching speeds through optimised gate layout with planar stripe DMOS technology. Application ■ Switching application Absolute Maximum Ratings Parameter Max. Units ID@Tc=25 ْ C Continuous Drain Current,VGS@10V 8 ID@Tc=100 ْC Continuous Drain Current,VGS@10V 5.1 IDM Pulsed Drain Current ① 32 A PD@TC=25 ْC Power Dissipation 125 W Linear Derating Factor 1.0 W/ ْC VGS Gate-to-Source Voltage ±30 V EAS Single Pulse Avalanche Energy ② 510 mJ IAR Avalanche Current ① 8 A EAR Repetitive Avalanche Energy ① 13 mJ dv/dt Peak Diode Recovery dv/dt ③ 5 V/ns TJ TSTG Operating Junction and Storage Temperature Range –55 to +175 Soldering Temperature, for 10 seconds 300(1.6mm from case) ْC Mounting Torque,6-32 or M3 screw 10 Ibf●in(1.1N●m) Thermal Resistance Parameter Min. Typ. Max. Units RθJC Junction-to-case — — 1.0 RθCS Case-to-Sink,Flat,Greased Surface — 0.50 — RθJA Junction-to-Ambient — — 62 ْC/W Pin1–Gate Pin2–Drain Pin1–Source VDSS = 500V ID25 = 8A RDS(ON) = 0.85Ω 1 |
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