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HM534253BJ-8 Datasheet(PDF) 9 Page - Elpida Memory |
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HM534253BJ-8 Datasheet(HTML) 9 Page - Elpida Memory |
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9 / 45 page  HM534253B Series Data Sheet E0165H10 9 RAS CAS Address WE DT/OE DSF I/O Color Register Set Cycle Flash Write Cycle Flash Write Cycle Row Xi Xj *1 *1 Color Data Set color register Execute flash write into each I/O on row address Xi using color resister. Execute flash write into each I/O on row address Xj using color resister. Note: 1. I/O Mask Data Low: Mask High: Non Mask Figure 1 Use of Flash Write Block Write Cycle ( CAS high, DT/OE high and DSF low at the falling edge of RAS, DSF high at the falling edge of CAS) In a block write cycle, 4 columns of data (4-word × 4-bit) are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are disregarded. The data on I/Os and addresses can be masked. I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) In a page mode cycle, mixed cycle of normal Read/Write and block write can be allowed by controlling DSF. • Normal Mode Block Write Cycle (WE high at the falling edge of RAS) The data on 4 I/Os are all cleared when WE is high at the falling edge of RAS. • Mask Block Write Mode (WE low at the falling edge of RAS) When WE is low at the falling edge of RAS, the HM534253B starts mask block write mode to clear the data on an optional I/O. The mask data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data is retained. The mask data is available in the RAS cycle. In page mode block write cycle, the mask data is retained during the page access. |
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