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HM5316123BF-7 Datasheet(PDF) 11 Page - Elpida Memory

Part # HM5316123BF-7
Description  131,072-word x 16-bit Multiport CMOS Video RAM
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5316123BF-7 Datasheet(HTML) 11 Page - Elpida Memory

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11
HM5316123B Series
Transfer Operation
The HM5316123B provides the read transfer
cycle, split read transfer cycle, masked write
transfer cycle and masked split write transfer cycle
as data transfer cycles. Theses transfer cycles are
set by driving
CAS high and DT/OE low at the
falling edge of
RAS. They have following
functions:
(1) Transfer data between row address and SAM
data register
Read transfer cycle and split read transfer cycle:
RAM to SAM
Masked write transfer cycle and masked split write
transfer cycle: SAM to RAM
(2) Determine SI/O state (except for split read
transfer cycle and masked split write transfer
cycle)
Read transfer cycle: SI/O output
Masked write transfer cycle: SI/O input
(3) Determine first SAM address to access after
transferring at column address (SAM start
address).
SAM start address must be determined by read
transfer cycle or masked write transfer cycle (split
transfer cycle isn’t available)before SAM access,
after power on, and determined for each transfer
cycle.
(4) Use the stopping columns (boundaries) in the
serial shift register. If the stopping columns have
been set, split transfer cycles use the stopping
columns, but any boundaries cannot be set as the
start address.
(5) Load/use mask data in masked write transfer
cycle and masked split write transfer cycle.
Read Transfer Cycle (
CAS high, DT/OE low,
WEU and WEL high and DSF1 low at the falling
edge of
RAS)
This cycle becomes read transfer cycle by driving
DT/OE low, WEU and WEL high and DSF1 low at
the falling edge of
RAS. The row address data
(256 x 16 bits) determined by this cycle is
transferred to SAM data register synchronously at
the rising edge of
DT/OE. After the rising edge of
DT/OE, the new address data outputs from SAM
start address determined by column address. In
read transfer cycle,
DT/OE must be risen to
transfer data from RAM to SAM.
This cycle can access SAM even during transfer
(real time read transfer). In this case, the timing
tSDD (min) specified between the last SAM access
before transfer and
DT/OE rising edge and tSDH
(min) specified between the first SAM access and
DT/OE rising edge must be satisfied. (See figure
3.)
When read transfer cycle is executed, SI/O
becomes output state by first SAM access. Input
must be set high impedance before tSZS (min) of
the first SAM access to avoid data contention.
RAS
CAS
Address
DT/OE
SC
SI/O
SAM Data before Transfer
SAM Data after Transfer
tSDD
tSDH
L
Xi
Yj
Yj
Yj + 1
DSF1
Figure 3 Real Time Read Transfer
Preliminary Data Sheet E0160H10


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