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EDD2504AJTA-7A Datasheet(PDF) 9 Page - Elpida Memory |
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EDD2504AJTA-7A Datasheet(HTML) 9 Page - Elpida Memory |
9 / 50 page EDD2504AJTA, EDD2508AJTA Preliminary Data Sheet E0145E50 (Ver. 5.0) 9 Timing Parameter Measured in Clock Cycle Number of clock cycle tCK 6ns 7.5ns Parameter Symbol min. max. min. max. Write to pre-charge command delay (same bank) tWPD 4 + BL/2 3 + BL/2 Read to pre-charge command delay (same bank) tRPD BL/2 BL/2 Write to read command delay (to input all data) tWRD 2 + BL/2 2 + BL/2 Burst stop command to write command delay (CL = 2) tBSTW 2 2 (CL = 2.5) tBSTW 3 3 Burst stop command to DQ High-Z (CL = 2) tBSTZ 2 2 2 2 (CL = 2.5) tBSTZ 2.5 2.5 2.5 2.5 Read command to write command delay (to output all data) (CL = 2) tRWD 2 + BL/2 2 + BL/2 (CL = 2.5) tRWD 3 + BL/2 3 + BL/2 Pre-charge command to High-Z (CL = 2) tHZP 2 2 2 2 (CL = 2.5) tHZP 2.5 2.5 2.5 2.5 Write command to data in latency tWCD 1 1 1 1 Write recovery tWR 3 2 DM to data in latency tDMD 0 0 0 0 Mode register set command cycle time tMRD 2 2 Self refresh exit to non-read command tSNR 12 10 Self refresh exit to read command tSRD 200 200 Power down entry tPDEN 1 1 1 1 Power down exit to command input tPDEX 1 1 |
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