EBR12UC8ABKD

Preliminary Data Sheet E0314E11 (Ver. 1.1)

5

Signal

Module

connector pads

I/O

Type

Description

ROW2_THRU_R..

ROW0_THRU_R

A52, B50, A50

I

RSL

Row bus. 3-bit bus containing control and address information

for row accesses. Connects to right RDRAM device on "Thru"

Channel.

SCK_THRU_L

A2

I

VCMOS

Serial Clock input. Clock source used to read from and write

to "Thru" Channel RDRAM control registers. Connects to left

RDRAM device on "Thru" Channel.

SCK_THRU_R

A71

I

VCMOS

Serial Clock input. Clock source used to read from and write

to "Thru" Channel RDRAM control registers. Connects to right

RDRAM device on "Thru" Channel.

SIN_THRU

B34

I/O

VCMOS

"Thru" Channel Serial I/O for reading from and writing to the

control registers. Attaches to SIO0 of right RDRAM device on

"Thru" Channel.

SOUT_THRU

A34

I/O

VCMOS

"Thru" Channel Serial I/O for reading from and writing to the

control registers. Attaches to SIO1 of left RDRAM device on

"Thru" Channel.

CFM_TERM

B103

I

RSL

Clock from master. Connects to right RDRAM device on

"Term" Channel. Interface clock used for receiving RSL

signals from the controller. Positive polarity.

CFMN_TERM

B101

I

RSL

Clock from master. Connects to right RDRAM device on

"Term" Channel. Interface clock used for receiving RSL

signals from the controller. Negative polarity.

CMD_TERM

A115

I

VCMOS

Serial Command Input used to read from and write to the

control registers. Also used for power management.

Connects to right RDRAM device on "Term" Channel.

COL4_TERM..

COL0_TERM

B97, A97, B95, A95,

B93

I

RSL

"Term" Channel Column bus. 5-bit bus containing control and

address information for column accesses. Connects to right

RDRAM device on "Term" Channel.

CTM_TERM_L

B73

I

RSL

Clock To Master. Connects to left RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to

the controller. Positive polarity.

CTM_TERM_R

A103

I

RSL

Clock To Master. Connects to right RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to

the controller. Positive polarity.

CTMN_TERM_L

B71

I

RSL

Clock To Master. Connects to left RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to

the controller. Negative polarity.

CTMN_TERM_R

A105

I

RSL

Clock To Master. Connects to right RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to

the controller. Negative polarity.

DQA8_TERM..

DQA0_TERM

B113, A113, B111,

A111, B109, A109,

B107, A107, B105

I/O

RSL

"Term" Channel Data bus A. A 9-bit bus carrying a byte of

read or write data between the controller and RDRAM devices

on “Term” Channel. Connects to right RDRAM device on

"Term" Channel.

DQB8_TERM..

DQB0_TERM

A85, B85, A87, B87,

A89, B89, A91, B91,

A93

I/O

RSL

"Term" Channel Data bus B. A 9-bit bus carrying a byte of

read or write data between the controller and RDRAM devices

on “Term” Channel. Connects to right RDRAM device on

"Term" Channel.

ROW2_TERM..

ROW0_TERM

A101, B99, A99

I

RSL

"Term" Channel Row bus. 3-bit bus containing control and

address information for row accesses. Connects to right

RDRAM device on "Term" Channel.

SCK_TERM

B115

I

VCMOS

Serial Clock input. Clock source used to read from and write

to "Term" Channel RDRAM control registers. Connects to

right RDRAM device on "Term" Channel.

SIN_TERM

B83

I/O

VCMOS

"Term" Channel Serial I/O for reading from and writing to the

control registers. Attaches to SIO0 of left RDRAM device on

"Term" Channel.

VTERM

A60, B60, A61, B61

"Term" Channel Termination voltage.