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HB54A2569F1U-B75B Datasheet(PDF) 1 Page - Elpida Memory |
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HB54A2569F1U-B75B Datasheet(HTML) 1 Page - Elpida Memory |
1 / 17 page Document No. E0206H30 (Ver. 3.0) Date Published September 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. DATA SHEET 256MB, 512MB Registered DDR SDRAM DIMM HB54A2569F1U (32M words ×××× 72 bits, 1 Bank) HB54A5129F2U (64M words ×××× 72 bits, 2 Banks) Description The HB54A2569F1U, HB54A5129F2U are Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425801BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2569F1U is organized as 32M × 72 × 1 bank mounted 9 pieces of 256M bits DDR SDRAM. The HB54A5129F2U is organized as 32M × 72 × 2 banks mounted 18 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. Features • 184-pin socket type package (dual lead out) Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness) Lead pitch: 1.27mm • 2.5V power supply (VCC/VCCQ) • SSTL-2 interface for all inputs and outputs • Clock frequency: 143MHz/133MHz/125MHz (max.) • Data inputs, outputs and DM are synchronized with DQS • 4 banks can operate simultaneously and independently (Component) • Burst read/write operation • Programmable burst length: 2, 4, 8 Burst read stop capability • Programmable burst sequence Sequential Interleave • Start addressing capability Even and Odd • Programmable /CAS latency (CL): 3, 3.5 • 8192 refresh cycles: 7.8µs (8192/64ms) • 2 variations of refresh Auto refresh Self refresh This product became EOL in May, 2004. |
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