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EBD52UC8AAFA-6B Datasheet(PDF) 7 Page - Elpida Memory |
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EBD52UC8AAFA-6B Datasheet(HTML) 7 Page - Elpida Memory |
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7 / 17 page  EBD52UC8AAFA-6B Preliminary Data Sheet E0392E10 (Ver. 1.0) 7 Block Diagram DQ DQS DM DQ0 to DQ7 * U1 to U8, U10 to U17: 256M bits DDR SDRAM U20: 2k bits EEPROM RS: 22 Ω Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. 8 DQS0 DM0/DQS9 RS RS RS /CS U1 /CS0 /CS1 DQ DQ8 to DQ15 8 DQS1 DM1/DQS10 RS RS RS U11 DQ DQ16 to DQ23 8 DQS2 DM2/DQS11 RS RS RS U3 DQ DQ24 to DQ31 8 DQS3 DM3/DQS12 RS RS RS U13 DQ DQ32 to DQ39 8 DQS4 DM4/DQS13 RS RS RS U14 DQ DQ40 to DQ47 8 DQS5 DM5/DQS14 RS RS RS U6 DQ DQ48 to DQ55 8 DQS6 DM6/DQS15 RS RS RS U16 DQ DQ56 to DQ63 8 DQS7 DM7/DQS16 RS RS RS U8 A0 to A12 (U1 to U8, U10 to U17) BA0, BA1 (U1 to U8, U10 to U17) /RAS (U1 to U8, U10 to U17) /CAS (U1 to U8, U10 to U17) /WE (U1 to U8, U10 to U17) CKE (U1 to U8, U10 to U17) CKE0 CKE (U1 to U8, U10 to U17) CKE1 U1 to U8, U10 to U17 U1 to U8, U10 to U17 U1 to U8, U10 to U17 VDD VSS VREF VDDID open Clock wiring Note: Wire per Clock loading table/Wiring diagrams. DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQ DQS DM /CS U10 DQ U2 DQ U12 DQ U4 DQ U5 DQ U15 DQ U7 DQ U17 DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS DQS DM /CS Clock input CK0, /CK0 CK1, /CK1 CK2, /CK2 DDR SDRAMS 4DRAM loads 6DRAM loads 6DRAM loads Serial PD SDA A0 A1 A2 SA0 SA1 SA2 SCL SCL U20 SDA A0 to A12 BA0, BA1 /RAS /CAS /WE 3.3 Ω 3.3 Ω 3.3 Ω 3.3 Ω 3.3 Ω |
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