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EBD52EC8AAFA Datasheet(PDF) 11 Page - Elpida Memory |
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EBD52EC8AAFA Datasheet(HTML) 11 Page - Elpida Memory |
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11 / 18 page  EBD52EC8AAFA Data Sheet E0363E20 (Ver. 2.0) 11 Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V) Parameter Symbol Pins max. Unit Notes Input capacitance CI1 Address, /RAS, /CAS, /WE, /CS, CKE 125 pF Input capacitance CI2 CK, /CK 85 pF Data and DQS input/output capacitance CO DQ, CB, DQS 20 pF AC Characteristics (TA = 0 to +70 °°°°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V) (DDR SDRAM Componen Specification) Parameter Symbol min. max Unit Notes Clock cycle time (CL = 2) tCK 10 15 ns (CL = 2.5) tCK 7.5 15 ns CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 tCK CK half period tHP min (tCH, tCL) — tCK DQ output access time from CK, /CK tAC –0.75 0.75 ns DQS output access time from CK, /CK tDQSCK –0.75 0.75 ns DQS to DQ skew tDQSQ — 0.5 ns DQ/DQS output hold time from DQS tQH tHP – 0.75 — ns Data-out high-impedance time from CK, /CK tHZ –0.75 0.75 ns 1 Data-out low-impedance time from CK, /CK tLZ –0.75 0.75 ns 1 Read preamble tRPRE 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 tCK DQ and DM input setup time tDS 0.5 — ns DQ and DM input hold time tDH 0.5 — ns DQ and DM input pulse width tDIPW 1.75 — ns Write preamble setup time tWPRES 0 — ns 3 Write preamble tWPRE 0.25 — tCK Write postamble tWPST 0.4 0.6 tCK 2 Write command to first DQS latching transition tDQSS 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 — tCK DQS falling edge hold time from CK tDSH 0.2 — tCK DQS input high pulse width tDQSH 0.35 — tCK DQS input low pulse width tDQSL 0.35 — tCK Address and control input setup time tIS 0.9 — ns 6 Address and control input hold time tIH 0.9 — ns 6 Mode register set command cycle time tMRD 15 — ns Active to Precharge command period tRAS 45 120000 ns Active to Active/Auto refresh command period tRC 65 — ns Auto refresh to Active/Auto refresh command period tRFC 75 — ns Active to Read/Write delay tRCD 20 — ns Precharge to active command period tRP 20 — ns |
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