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EDD2516KCTA-SI Datasheet(PDF) 1 Page - Elpida Memory |
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EDD2516KCTA-SI Datasheet(HTML) 1 Page - Elpida Memory |
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1 / 52 page  Document No. E0555E40 (Ver.4.0) Date Published December 2005 (K) Japan Printed in Japan URL: http://www.elpida.com ©Elpida Memory, Inc. 2004-2005 PRELIMINARY DATA SHEET 256M bits DDR SDRAM with Super Self-Refresh EDD2516KCTA-SI (16M words × 16 bits) Specifications • Density: 256M bits • Organization ⎯ 4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5 • Precharge: auto precharge operation for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, super self-refresh with Auto Temperature Compensated Self-refresh (ATCSR) function • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.8μs • Operating ambient temperature range ⎯ TA = −40°C to +85°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • SSR Flag function available Pin Configurations /xxx indicates active low signal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS SF VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS Address input Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection SSR Flag A0 to A12 BA0, BA1 DQ0 to DQ15 UDQS/LDQS /CS /RAS /CAS /WE UDM/LDM CK /CK CKE VREF VDD VSS VDDQ VSSQ NC SF 66-pin Plastic TSOP(II) (Top view) This product became EOL in April, 2007. |
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