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EDS2532AABH-1AR2 Datasheet(PDF) 7 Page - Elpida Memory |
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EDS2532AABH-1AR2 Datasheet(HTML) 7 Page - Elpida Memory |
7 / 48 page EDS2532AABH-1AR2 Data Sheet E0517E20 (Ver. 2.0) 7 AC Characteristics (TA = 0 to +70 °C, VDD, VDDQ = 3.1V to 3.5V, VSS, VSSQ = 0V) -1AR2 Parameter Symbol min. max. Unit Notes System clock cycle time (CL = 2) tCK 10 — ns 1 (CL = 3) tCK 10 — ns 1 CLK high pulse width tCH 3 — ns 1 CLK low pulse width tCL 3 — ns 1 Access time from CLK tAC — 6 ns 1, 2 Data-out hold time tOH 2.0 — ns 1, 2 CLK to Data-out low impedance tLZ 0 — ns 1, 2, 3 CLK to Data-out high impedance tHZ — 6 ns 1, 4 Input setup time tSI 2.0 — ns 1 Input hold time tHI 1.0 — ns 1 Ref/Active to Ref/Active command period tRC 70 — ns 1 Active to Precharge command period tRAS 50 120000 ns 1 Active command to column command (same bank) tRCD 20 — ns 1 Precharge to active command period tRP 20 — ns 1 Write recovery or data-in to precharge lead time tDPL 20 — ns 1 Last data into active latency tDAL 2CLK + 20ns — Active (a) to Active (b) command period tRRD 20 — ns 1 Transition time (rise and fall) tT 0.5 5.0 ns Refresh period (4096 refresh cycles) tREF — 32 ms Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V. 2. Access time is measured at 1.4V. Load condition is CL = 30pF. 3. tLZ (min.) defines the time at which the outputs achieves the low impedance state. 4. tHZ (max.) defines the time at which the outputs achieves the high impedance state. |
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