ECS1232ABCN-A datasheet(5/46 Pages) ELPIDA

Part #	ECS1232ABCN-A

Description	128M bits SDRAM Bare Chip

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Manufacturer	ELPIDA [Elpida Memory]

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ECS1232ABCN-A

Data Sheet E0486E30 (Ver. 3.0)

5

DC Characteristics 1 (TA = 0 to +70

°C, VDD, VDDQ = 3.0V to 3.6V, VSS, VSSQ = 0V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Notes

Operating current

IDD1

105

mA

Burst length = 1

tRC = tRC (min.)

1, 2, 3

Standby current in power down

IDD2P

3

mA

CKE = VIL,

tCK = tCK (min.)

6

Standby current in power down

(input signal stable)

IDD2PS

2

mA

CKE = VIL, tCK =

∞

7

Standby current in non power

down

IDD2N

20

mA

CKE, /CS = VIH,

tCK = tCK (min.)

4

Standby current in non power

down (input signal stable)

IDD2NS

9

mA

CKE = VIH, tCK =

∞,

/CS = VIH

8

Active standby current in power

down

IDD3P

4

mA

CKE = VIL,

tCK = tCK (min.)

1, 2, 6

Active standby current in power

down (input signal stable)

IDD3PS

3

mA

CKE = VIL, tCK =

∞

2, 7

Active standby current in non

power down

IDD3N

45

mA

CKE, /CS = VIH,

tCK = tCK (min.)

1, 2, 4

Active standby current in non

power down (input signal stable)

IDD3NS

30

mA

CKE = VIH, tCK =

∞,

/CS = VIH

2, 8

Burst operating current

IDD4

155

mA

tCK = tCK (min.),

BL = 4

1, 2, 5

Refresh current

IDD5

210

mA

tRC = tRC (min.)

3

Self refresh current

IDD6

2

mA

VIH ≥ VDD – 0.2V

VIL ≤ 0.2V

Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output

open condition.

2. One bank operation.

3. Input signals are changed once per one clock.

4. Input signals are changed once per two clocks.

5. Input signals are changed once per four clocks.

6. After power down mode, CLK operating current.

7. After power down mode, no CLK operating current.

8. Input signals are VIH or VIL fixed.

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