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EDS2732CABJ Datasheet(PDF) 8 Page - Elpida Memory

Part # EDS2732CABJ
Description  256M bits SDRAM
Download  48 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDS2732CABJ Datasheet(HTML) 8 Page - Elpida Memory

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EDS2732CABJ
Data Sheet E0462E30 (Ver. 3.0)
8
Test Conditions
• Input and output timing reference levels: 1.2V
• Input waveform and output load: See following figures
tT
2.1V
1.7V
0.7V
0.3V
input
tT
I/O
CL
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-75
-1A
Frequency (MHz)
133
100
tCK (ns)
Symbol
7.5
10
Unit
Notes
Active command to column command
(same bank)
lRCD
3
2
tCK
1
Active command to active command
(same bank)
lRC
9
7
tCK
1
Active command to precharge command
(same bank)
lRAS
6
5
tCK
1
Precharge command to active command
(same bank)
lRP
3
2
tCK
1
Write recovery or data-in to precharge
command (same bank)
lDPL
2
2
tCK
1
Active command to active command
(different bank)
lRRD
2
2
tCK
1
Self refresh exit time
lSREX
1
1
tCK
2
Last data in to active command
(Auto precharge, same bank)
lDAL
5
4
tCK
= [lDPL + lRP]
Self refresh exit to command input
lSEC
9
7
tCK
= [lRC]
3
Precharge command to high impedance
(CL = 2)
lHZP
2
2
tCK
(CL = 3)
lHZP
3
3
tCK
Last data out to active command
(Auto precharge, same bank)
lAPR
1
1
tCK
Last data out to precharge (early
precharge)
(CL = 2)
lEP
–1
–1
tCK
(CL = 3)
lEP
–2
–2
tCK
Column command to column command
lCCD
1
1
tCK
Write command to data in latency
lWCD
0
0
tCK
DQM to data in
lDID
0
0
tCK
DQM to data out
lDOD
2
2
tCK
CKE to CLK disable
lCLE
1
1
tCK
Register set to active command
lMRD
2
2
tCK
/CS to command disable
lCDD
0
0
tCK
Power down exit to command input
lPEC
1
1
tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]


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