EBD51RC4AAFA-7B datasheet(1/17 Pages) ELPIDA

Part #	EBD51RC4AAFA-7B

Description	512MB Registered DDR SDRAM DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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Document No. E0274E40 (Ver. 4.0)

Date Published April 2003 (K) Japan

URL: http://www.elpida.com

Elpida Memory,Inc. 2002-2003

PRELIMINARY DATA SHEET

1GB Registered DDR SDRAM DIMM

EBD10RD4ABFA (128M words

×××× 72 bits, 1 Rank)

Description

The EBD10RD4ABFA is 128M words

× 72 bits, 1 rank

Double Data Rate (DDR) SDRAM registered module,

mounting 18 pieces of 512M bits DDR SDRAM sealed

in TSOP package.

Read and write operations are

performed at the cross points of the CK and the /CK.

This high-speed data transfer is realized by the 2-bit

prefetch-pipelined architecture.

Data strobe (DQS)

both for read and write are available for high speed and

reliable data bus design. By setting extended mode

register, the on-chip Delay Locked Loop (DLL) can be

set enable or disable.

This module provides high

density mounting without utilizing surface mount

technology.

Decoupling capacitors are mounted

beside each TSOP on the module board.

Features

• 184-pin socket type dual in line memory module

(DIMM)

 PCB height: 30.48mm

 Lead pitch: 1.27mm

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs and outputs are synchronized with DQS

• 4 internal banks for concurrent operation

(Component)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

 7.8µs maximum average periodic refresh interval

• 2 variations of refresh

 Auto refresh

 Self refresh

• 1 piece of PLL clock driver, 2 pieces of register driver

and 1 piece of serial EEPROM (2k bits) for Presence

Detect (SPD) on PCB.

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