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EBD12RB8ALFB-75 Datasheet(PDF) 1 Page - Elpida Memory |
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EBD12RB8ALFB-75 Datasheet(HTML) 1 Page - Elpida Memory |
1 / 17 page Document No. E0235E10 (Ver. 1.0) Date Published October 2001 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001 C DATA SHEET 128MB Registered DDR SDRAM DIMM EBD12RB8ALFB (16M words ×××× 72 bits, 1 Bank) Description The EBD12RB8ALFB is a 16M × 72 × 1 bank Double Data Rate (DDR) SDRAM Module, mounted 9 pieces of 128M bits DDR SDRAM (EDD1208ALTA) sealed in TSOP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CLK and the /CLK. This high-speed data transfer is realized by the 2bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. Features • 184-pin socket type dual in line memory module (DIMM) Outline: 133.35mm (Length) × 30.48mm (Height) × 4.00mm (Thickness) Lead pitch: 1.27mm • 2.5V power supply (VDD/VDDQ) • SSTL-2 interface for all inputs and outputs • Clock frequency: 133MHz/100MHz (max.) • Data inputs and outputs are synchronized with DQS • 4 banks can operate simultaneously and independently (Component) • Burst read/write operation • Programmable burst length: 2, 4, 8 Burst read stop capability • Programmable burst sequence Sequential Interleave • Start addressing capability Even and Odd • Programmable /CAS latency (CL): 2, 2.5 • 4096 refresh cycles: 15.6µs (4096/64ms) • 2 variations of refresh Auto refresh Self refresh |
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