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EBD12UB8ALF-7A Datasheet(PDF) 6 Page - Elpida Memory

Part # EBD12UB8ALF-7A
Description  128MB Unbuffered DDR SDRAM DIMM
Download  16 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD12UB8ALF-7A Datasheet(HTML) 6 Page - Elpida Memory

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EBD12UB8ALF
Preliminary Data Sheet E0216E10 (Ver. 1.0)
6
Byte No.
Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex value
Comments
27
Minimum row precharge time (tRP)
-7A
0
1
0
1
0
0
0
0
50H
20ns
-75
0
1
0
1
0
0
0
0
50H
20ns
-1A
0
1
0
1
0
0
0
0
50H
20ns
28
Minimum row active to row active
delay (tRRD)
-7A
0
0
1
1
1
1
0
0
3CH
15ns
-75
0
0
1
1
1
1
0
0
3CH
15ns
-1A
0
0
1
1
1
1
0
0
3CH
15ns
29
Minimum /RAS to /CAS delay (tRCD)
-7A
0
1
0
1
0
0
0
0
50H
20ns
-75
0
1
0
1
0
0
0
0
50H
20ns
-1A
0
1
0
1
0
0
0
0
50H
20ns
30
Minimum active to precharge time
(tRAS)
-7A
0
0
1
0
1
1
0
1
2DH
45ns
-75
0
0
1
0
1
1
0
1
2DH
45ns
-1A
0
0
1
1
0
0
1
0
32H
50ns
31
Module bank density
0
0
1
0
0
0
0
0
20H
128M bytes
32
Address and command setup time
before clock (tIS)
-7A
1
0
0
1
0
0
0
0
90H
0.9ns
-75
1
0
0
1
0
0
0
0
90H
0.9ns
-1A
1
0
1
1
0
0
0
0
B0H
1.1ns
33
Address and command hold time after
clock (tIH)
-7A
1
0
0
1
0
0
0
0
90H
0.9ns
-75
1
0
0
1
0
0
0
0
90H
0.9ns
-1A
1
0
1
1
0
0
0
0
B0H
1.1ns
34
Data input setup time before clock
(tDS)
-7A
0
1
0
1
0
0
0
0
50H
0.5ns
-75
0
1
0
1
0
0
0
0
50H
0.5ns
-1A
0
1
1
0
0
0
0
0
60H
0.6ns
35
Data input hold time after clock (tDH)
-7A
0
1
0
1
0
0
0
0
50H
0.5ns
-75
0
1
0
1
0
0
0
0
50H
0.5ns
-1A
0
1
1
0
0
0
0
0
60H
0.6ns
36 to 61
Superset information
0
0
0
0
0
0
0
0
00H
62
SPD Revision
0
0
0
0
0
0
0
0
00H
63
Checksum for bytes 0 to 62
-7A
0
1
1
1
0
0
0
1
71H
-75
1
0
0
1
1
1
0
0
9CH
-1A
0
1
0
0
0
0
1
0
42H
64
Manufacturer’s JEDEC ID code
1
1
1
1
1
1
1
0
FEH
Elpida Memory
65 to 71
Manufacturer’s JEDEC ID code
72
Manufacturing location
73 to 90
Manufacturer’s part number
91 to 92
Revision code
93 to 94
Manufacturing date


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