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MC-45D32DC721KFA-C75 Datasheet(PDF) 1 Page - Elpida Memory |
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MC-45D32DC721KFA-C75 Datasheet(HTML) 1 Page - Elpida Memory |
1 / 16 page The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. MOS INTEGRATED CIRCUIT MC-45D32DC721 Document No. E0036N10 (1st edition) (Previous No. M14790EJ3V0DS00) Date Published January 2001 CP (K) Printed in Japan PRELIMINARY DATA SHEET 32 M-WORD BY 72-BIT DDR SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. Description The MC-45D32DC721 is a 33,554,432 words by 72 bits DDR synchronous dynamic RAM module on which 18 pieces of 128M DDR SDRAM: µPD45D128842 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features • 33,554,432 words by 72 bits organization (ECC type) • Clock frequency Part number /CAS latency Clock frequency Module type (MAX.) MC-45D32DC721KF-C75 CL = 2.5 133 MHz DDR Registered DIMM CL = 2 100 MHz Design specification Rev. 0.6 compliant MC-45D32DC721KF-C80 CL = 2.5 125 MHz CL = 2 100 MHz MC-45D32DC721KFA-C75 CL = 2.5 133 MHz DDR Registered DIMM CL = 2 100 MHz Design specification Rev. 0.9 compliant MC-45D32DC721KFA-C80 CL = 2.5 125 MHz CL = 2 100 MHz • Fully Synchronous Dynamic RAM with all signals except DM, DQS and DQ referenced to a positive clock edge • Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK • Quad internal banks operation • Possible to assert random column address in every clock cycle • Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh |
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