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EBE21FD4AGFN-5C-E Datasheet(PDF) 4 Page - Elpida Memory |
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EBE21FD4AGFN-5C-E Datasheet(HTML) 4 Page - Elpida Memory |
4 / 22 page EBE21FD4AGFD, EBE21FD4AGFN Preliminary Data Sheet E0868E30 (Ver. 3.0) 4 Advanced Memory Buffer Block Diagram Demux PISO Mux Mux Mux Mux Link init SM and control and CSRs Link init SM and control and CSRs Sync & idle pattern generator IBIST-TX failover failover DRAM Command Command out DRAM clock 4 DRAM data and strobes DRAM address and command copy1 Data in Data out PLL Reset control Thermal sensor DRAM interface Core controller and CSRs LAI controller SMBus controller Command decoder & CRC check Data CRC generator and Read FIFO Reference clock /RESET SMBus Write data FIFO LAI logic NB LAI Buffer Init patterns DDR state controller and CSRs External MemBIST DDR calibration Re-synch 10 ×2 1 ×2 RE-time Southbound Data in 10 ×2 10 ×12 10 ×12 Southbound Data out Data merge PISO Re-synch 14 ×6×2 RE-time Northbound Data Out Northbound Data In 14 ×214×2 14 ×12 Demux DRAM clock 4 29 DRAM address and command copy2 29 72+18 ×2 Data merge IBIST-RX IBIST-RX IBIST-TX Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains. |
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