EBE51RD8AEFA-6 datasheet(5/22 Pages) ELPIDA

Part #	EBE51RD8AEFA-6

Description	512MB Registered DDR2 SDRAM DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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EBE51RD8AEFA-6

Data Sheet E0789E11 (Ver. 1.1)

5

Serial PD Matrix*

1

Byte No.

Function described

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Hex value

Comments

0

Number of bytes utilized by module

manufacturer

1

0

80H

128 bytes

1

Total number of bytes in serial PD

device

0

1

0

08H

256 bytes

2

Memory type

0

1

0

08H

DDR2 SDRAM

3

Number of row address

0

1

0

0EH

14

4

Number of column address

0

1

0

1

0

0AH

10

5

Number of DIMM ranks

0

1

0

60H

1

6

Module data width

0

1

0

1

0

48H

72

7

Module data width continuation

0

00H

0

8

Voltage interface level of this assembly 0

0

1

0

1

05H

SSTL 1.8V

9

DDR SDRAM cycle time, CL = 5

0

1

0

30H

3.0ns*

1

10

SDRAM access from clock (tAC)

0

1

0

1

0

1

45H

0.45ns*

1

11

DIMM configuration type

0

1

0

02H

ECC

12

Refresh rate/type

1

0

1

0

82H

7.8

µs

13

Primary SDRAM width

0

1

0

08H

× 8

14

Error checking SDRAM width

0

1

0

08H

× 8

15

Reserved

0

00H

0

16

SDRAM device attributes:

Burst length supported

0

1

0

0CH

4,8

17

SDRAM device attributes: Number of

banks on SDRAM device

0

1

0

04H

4

18

SDRAM device attributes:

/CAS latency

0

1

0

38H

3, 4, 5

19

DIMM Mechanical Characteristics

0

1

01H

4.00mm max.

20

DIMM type information

0

1

01H

Registered

21

SDRAM module attributes

0

00H

Normal

22

SDRAM device attributes: General

0

1

03H

Weak Driver

50

Ω ODT

Support

23

Minimum clock cycle time at CL = 4

0

1

0

1

3DH

3.75ns*

1

24

Maximum data access time (tAC) from

clock at CL = 4

0

1

0

1

0

50H

0.5ns*

1

25

Minimum clock cycle time at CL = 3

0

1

0

1

0

50H

5.0ns*

1

26

Maximum data access time (tAC) from

clock at CL = 3

0

1

0

60H

0.6ns*

1

27

Minimum row precharge time (tRP)

0

1

0

3CH

15ns

28

Minimum row active to row active

delay (tRRD)

0

1

0

1EH

7.5ns

29

Minimum /RAS to /CAS delay (tRCD)

0

1

0

3CH

15ns

30

Minimum active to precharge time

(tRAS)

0

1

0

1

0

1

2DH

45ns

31

Module rank density

1

0

80H

512M byte

32

Address and command setup time

before clock (tIS)

0

1

0

20H

0.20ns*

1

33

Address and command hold time after

clock (tIH)

0

1

0

1

0

28H

0.28ns*

1

34

Data input setup time before clock

(tDS)

0

1

0

10H

0.10ns*

1

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