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EBE10EE8ACFA-8G-E Datasheet(PDF) 1 Page - Elpida Memory |
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EBE10EE8ACFA-8G-E Datasheet(HTML) 1 Page - Elpida Memory |
1 / 30 page Document No. E1059E20 (Ver. 2.0) Date Published December 2007 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007 DATA SHEET 1GB Unbuffered DDR2 SDRAM DIMM EBE10EE8ACFA (128M words × 72 bits, 1 Rank) Specifications • Density: 1GB • Organization 128M words × 72 bits, 1 rank • Mounting 9 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms Average refresh period 7.8 µs at 0°C ≤ TC ≤ +85°C 3.9 µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation |
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