EBE51ED8AJWA datasheet(6/29 Pages) ELPIDA

Part #	EBE51ED8AJWA

Description	512MB Unbuffered DDR2 SDRAM DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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6 / 29 page

EBE51ED8AJWA

Data Sheet E1056E30 (Ver. 3.0)

6

Byte No.

Function described

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Hex value Comments

26

Maximum data access time (tAC) from

clock at CL = X

− 2

-8E, -6E (CL = 3)

0

1

0

60H

0.6ns*

1

-8G (CL = 4)

0

1

0

1

0

50H

0.5ns*

1

27

Minimum row precharge time (tRP)

-8E

0

1

0

1

0

32H

12.5ns

-8G, -6E

0

1

0

3CH

15ns

28

Minimum row active to row active delay

(tRRD)

0

1

0

1EH

7.5ns

29

Minimum /RAS to /CAS delay (tRCD)

-8E

0

1

0

1

0

32H

12.5ns

-8G, -6E

0

1

0

3CH

15ns

30

Minimum active to precharge time

(tRAS)

0

1

0

1

0

1

2DH

45ns

31

Module rank density

1

0

80H

512M bytes

32

Address and command setup time

before clock (tIS)

-8E, -8G

0

1

0

1

17H

0.17ns*

1

-6E

0

1

0

20H

0.20ns*

1

33

Address and command hold time after

clock (tIH)

-8E, -8G

0

1

0

1

0

1

25H

0.25ns*

1

-6E

0

1

0

1

27H

0.27ns*

1

34

Data input setup time before clock

(tDS)

-8E, -8G

0

1

0

1

05H

0.05ns*

1

-6E

0

1

0

10H

0.10ns*

1

35

Data input hold time after clock (tDH)

-8E, -8G

0

1

0

1

0

12H

0.12ns*

1

-6E

0

1

0

1

17H

0.17ns*

1

36

Write recovery time (tWR)

0

1

0

3CH

15ns*

1

37

Internal write to read command delay

(tWTR)

0

1

0

1EH

7.5ns*

1

38

Internal read to precharge command

delay (tRTP)

0

1

0

1EH

7.5ns*

1

39

Memory analysis probe characteristics 0

0

00H

TBD

40

Extension of Byte 41 and 42

-8E

0

1

0

30H

-8G, -6E

0

00H

Undefined

41

Active command period (tRC)

-8E

0

1

0

1

39H

57.5ns*

1

-8G, -6E

0

1

0

3CH

60ns*

1

42

Auto refresh to active/

Auto refresh command cycle (tRFC)

0

1

0

1

0

1

69H

105ns*

1

43

SDRAM tCK cycle max. (tCK max.)

1

0

80H

8ns*

1

44

Dout to DQS skew

-8E, -8G

0

1

0

1

0

14H

0.20ns*

1

-6E

0

1

0

18H

0.24ns*

1

45

Data hold skew (tQHS)

-8E, -8G

0

1

0

1EH

0.30ns*

1

-6E

0

1

0

1

0

22H

0.34ns*

1

46

PLL relock time

0

00H

Undefined

47 to 61

0

00H

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