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| EBE11ED8AGWA-5C-E |
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12 page 
EBE11ED8AGWA Preliminary Data Sheet E0920E10 (Ver. 1.0) 12 Parameter Symbol Grade max. Unit Test condition Self-refresh current IDD6 108 mA Self Refresh Mode; CK and /CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating current (Bank interleaving) (Another rank is in IDD2P) IDD7 -6E -5C 2970 2970 mA Operating current (Bank interleaving) (Another rank is in IDD3N) IDD7 -6E -5C 3510 3465 mA all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 × tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W; Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Input Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN ≤ VIL (AC) (max.) H is defined as VIN ≥ VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions. AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized. DDR2-667 DDR2-533 Parameter 5-5-5 4-4-4 Unit CL(IDD) 5 4 tCK tRCD(IDD) 15 15 ns tRC(IDD) 60 60 ns tRRD(IDD) 7.5 7.5 ns tCK(IDD) 3 3.75 ns tRAS(min.)(IDD) 45 45 ns tRAS(max.)(IDD) 70000 70000 ns tRP(IDD) 15 15 ns tRFC(IDD) 105 105 ns |
