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M68000PM Datasheet(PDF) 4 Page - Motorola, Inc |
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M68000PM Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 26 page 4 M68000 USER’S MANUAL ADDENDUM MOTOROLA 2.0 SIGNAL DESCRIPTION Change Figure 3-3 on Page 3-2. Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000) 2.1 Data Bus (D15-D0) In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15- D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.” 2.2 Bus Arbitration Control In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.” 2.3 System Control The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/ 68EC000/68SEC000).’’ 2.4 MC68SEC000 Low-Power Mode Add the following to Sections 4 and 5, Bus Operation. The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the ADDRESS BUS DATA BUS ASYNCHRONOUS BUS CONTROL BUS ARBITRATION CONTROL INTERRUPT CONTROL PROCESSOR STATUS A23-A0 D15-D0 AS R/W UDS LDS DTACK BERR RESET HALT MODE SYSTEM CONTROL VCC GND CLK MC68SEC000 FC0 FC1 FC2 IPL0 IPL1 IPL2 AVEC BR BG |
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