EBE21UE8ACUA-8G-E datasheet(11/27 Pages) ELPIDA

Part #	EBE21UE8ACUA-8G-E

Description	2GB DDR2 SDRAM SO-DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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11 / 27 page

EBE21UE8ACUA

Data Sheet E1217E10 (Ver. 1.0)

11

DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)

Parameter

Symbol

Grade

max.

Unit

Test condition

Operating current

(ACT-PRE)

(Another rank is in IDD2P)

IDD0

-8E, -8G

-6E

760

720

mA

Operating current

(ACT-PRE)

(Another rank is in IDD3N)

IDD0

-8E, -8G

-6E

1400

1280

mA

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(ACT-READ-PRE)

(Another rank is in IDD2P)

IDD1

-8E, -8G

-6E

880

840

mA

Operating current

(ACT-READ-PRE)

(Another rank is in IDD3N)

IDD1

-8E, -8G

-6E

1520

1400

mA

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Precharge power-down

standby current

IDD2P

160

mA

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Precharge quiet standby

current

IDD2Q

-8E, -8G

-6E

560

480

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

Idle standby current

IDD2N

-8E, -8G

-6E

640

560

mA

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

IDD3P-F

560

mA

Fast PDN Exit

MRS(12) = 0

Active power-down

standby current

IDD3P-S

320

mA

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address bus

inputs are STABLE;

Data bus inputs are FLOATING

Slow PDN Exit

MRS(12) = 1

Active standby current

IDD3N

-8E, -8G

-6E

1440

1280

mA

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

(Burst read operating)

(Another rank is in IDD2P)

IDD4R

-8E, -8G

-6E

1360

1200

mA

Operating current

(Burst read operating)

(Another rank is in IDD3N)

IDD4R

-8E, -8G

-6E

2000

1760

mA

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

(Burst write operating)

(Another rank is in IDD2P)

IDD4W

-8E, -8G

-6E

1360

1200

mA

Operating current

(Burst write operating)

(Another rank is in IDD3N)

IDD4W

-8E, -8G

-6E

2000

1760

mA

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

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