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EDD2532DGBH-7FTT-F Datasheet(PDF) 6 Page - Elpida Memory

Part # EDD2532DGBH-7FTT-F
Description  256M bits DDR Mobile RAM??WTR (Wide Temperature Range)
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EDD2532DGBH-7FTT-F Datasheet(HTML) 6 Page - Elpida Memory

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EDD2532DGBH-TT
Preliminary Data Sheet E1201E20 (Ver. 2.0)
6
DC Characteristics 1 (TA = –20
°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V)
Parameter
Symbol
Grade
max.
Unit
Test condition
Notes
Operating current
IDD1
-6C
-7F
65
65
mA
Burst length = 2
tRC
≥ tRC (min.), IO = 0mA,
One bank active
1
Standby current in power-down
IDD2P
-6C
-7F
0.8
0.8
mA
CKE
≤ VIL (max.),
tCK = tCK (min.)
Standby current in power-down
(input signal stable)
IDD2PS
0.6
mA
CKE
≤ VIL (max.), tCK = ∞
Standby current in non power-down
IDD2N
-6C
-7F
10
10
mA
CKE
≥ VIH (min.),
tCK = tCK (min.),
/CS
≥ VIH (min.),
Input signals are changed one time
during 2tCK.
Standby current in non power-down
(input signal stable)
IDD2NS
4.0
mA
CKE
≥ VIH (min.), tCK = ∞,
Input signals are stable.
Active standby current in power-down IDD3P
-6C
-7F
4.0
4.0
mA
CKE
≤ VIL (max.),
tCK = tCK (min.)
Active standby current in power-down
(input signal stable)
IDD3PS
3.0
mA
CKE
≤ VIL (max.), tCK = ∞
Active standby current in non power-
down
IDD3N
-6C
-7F
15
15
mA
CKE
≥ VIH (min.),
tCK = tCK (min.),
/CS
≥ VIH (min.),
Input signals are changed one time
during 2 tCK.
Active standby current in non power-
down
(input signal stable)
IDD3NS
10
mA
CKE
≥ VIH (min.), tCK = ∞,
Input signals are stable.
Burst operating current
IDD4
-6C
-7F
135
110
mA
Burst length = 4
tCK
≥ tCK (min.),
IOUT = 0mA, All banks active
2
Refresh current
IDD5
-6C
-7F
110
100
mA
tRFC
≥ tRFC (min.)
3
Self-refresh current
IDD6
3.0
mA
CKE
≤ 0.2V
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD1 is measured on condition that addresses are changed only one time during
tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured on condition that addresses are changed only one time during
tCK (min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).


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