EDE2104ABSE-8G-E datasheet(1/81 Pages) ELPIDA

Part #	EDE2104ABSE-8G-E

Description	2G bits DDR2 SDRAM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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Document No. E1196E30 (Ver.3.0)

Date Published December 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2007-2008

DATA SHEET

2G bits DDR2 SDRAM

EDE2104ABSE (512M words

× 4 bits)

EDE2108ABSE (256M words

× 8 bits)

Specifications

• Density: 2G bits

• Organization

 64M words × 4 bits × 8 banks (EDE2104ABSE)

 32M words × 8 bits × 8 banks (EDE2108ABSE)

• Package

 68-ball FBGA

 Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate

 800Mbps/667Mbps/533Mbps (max.)

• 1KB page size

 Row address: A0 to A14

 Column address: A0 to A9, A11 (EDE2104ABSE)

A0 to A9 (EDE2108ABSE)

• Eight internal banks for concurrent operation

• Interface: SSTL_18

• Burst lengths (BL): 4, 8

• Burst type (BT):

 Sequential (4, 8)

 Interleave (4, 8)

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

 Average refresh period

7.8

µs at 0°C ≤ TC ≤ +85°C

3.9

µs at +85°C < TC ≤ +95°C

• Operating case temperature range

 TC = 0°C to +95°C

Features

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to

× 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

Similar Part No. - EDE2104ABSE-8G-E

Manufacturer	Part #	Datasheet	Description
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EDE2104ABSE-8G-E Datasheet(PDF) 1 Page - Elpida Memory

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