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EDK1216CFBJ-75-F Datasheet(PDF) 6 Page - Elpida Memory |
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EDK1216CFBJ-75-F Datasheet(HTML) 6 Page - Elpida Memory |
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6 / 56 page  EDK1216CFBJ Preliminary Data Sheet E1194E20 (Ver. 2.0) 6 Notes: 1. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured on condition that addresses are changed only one time during tCK (min.). 2. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). DC Characteristics 2 (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V) Parameter Symbol min. max. Unit Test condition Notes Input leakage current ILI –2.0 2.0 µA 0 ≤ VIN ≤ VDDQ Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDDQ, DQ = disable Output high voltage VOH 0.9 × VDDQ — V IOH = − 0.1mA Output low voltage VOL — 0.1 × VDDQ V IOL = 0.1 mA Pin Capacitance (TA = +25°C, VDD and VDDQ = 1.7V to 1.95V) Parameter Symbol Pins min. typ. max. Unit Notes Input capacitance CI1 CK, /CK 1.5 — 3.5 pF 1 CI2 All other input-only pins 1.5 — 3.0 pF 1 Delta input capacitance Cdi1 CK, /CK — — 0.25 pF 1 Cdi2 All other input-only pins — — 0.5 pF 1 Input/output capacitance CI/O DQ, DM, DQS 2.0 — 4.5 pF 1, 2 Delta input/output capacitance Cdio DQ, DM, DQS — — 0.5 pF 1 Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V, TA = +25 °C. 2. DOUT circuits are disabled. AC Characteristics (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V) Parameter Symbol min. max. Unit Notes Clock cycle time tCK 7.5 100 ns CK high-level width tCH 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 tCK CK half period tHP min. ( tCH, tCL) — tCK DQ output access time from CK, /CK tAC 2.5 6.0 ns 2, 8 DQS-in cycle time tDSC 0.9 1.1 tCK DQS output access time from CK, /CK tDQSCK 2.5 6.0 ns 2, 8 DQ-out high-impedance time from CK, /CK tHZ — 6.0 ns 5, 8 DQ-out low-impedance time from CK, /CK tLZ 1.0 — ns 6, 8 DQS to DQ skew tDQSQ — 0.6 ns 3 DQ/DQS output hold time from DQS tQH tHP − tQHS — ns 4 Data hold skew factor tQHS — 0.75 ns DQ and DM input setup time tDS 0.8 — ns 3 DQ and DM input hold time tDH 0.8 — ns 3 DQ and DM input pulse width tDIPW 1.8 — ns Read preamble tRPRE 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 tCK Write preamble setup time tWPRES 0 — ns Write preamble tWPRE 0.25 — tCK Write postamble tWPST 0.4 0.6 tCK 7 |
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