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EDK1216CFBJ Datasheet(PDF) 9 Page - Elpida Memory |
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EDK1216CFBJ Datasheet(HTML) 9 Page - Elpida Memory |
9 / 56 page EDK1216CFBJ Preliminary Data Sheet E1194E20 (Ver. 2.0) 9 Timing Parameter Measured in Clock Cycle Number of clock cycle tCK 7.5ns Parameter Symbol min. max. Unit Notes Write to pre-charge command delay (same bank) tWPD 3 + BL/2 tCK Read to pre-charge command delay (same bank) tRPD BL/2 tCK Write to read command delay (to input all data) tWRD 2 + BL/2 tCK Burst stop command to write command delay (CL = 3) tBSTW 3 tCK Burst stop command to DQ high-Z (CL = 3) tBSTZ 3 tCK Read command to write command delay (to output all data) (CL = 3) tRWD 3 + BL/2 tCK Pre-charge command to high-Z (CL = 3) tHZP 3 tCK Write command to data in latency tWCD 1 tCK Write recovery tWR 2 tCK DM to data in latency tDMD 0 tCK Mode register set command cycle time tMRD 2 tCK Self-refresh exit to non-column command tSREX 16 tCK Auto refresh period tRFC 13 tCK Power down entry tPDEN 2 tCK 1 Power down exit to command input tPDEX 1 tCK 2 CKE minimum pulse width tCKE 1 tCK 2 Notes: 1. The device will be into power down mode at the second CK rising edge after CKE to be low level with NOP or DESL command. 2. If PDEN command is issued but CKE stay in low level just for one clock (=tCKE min.) then CKE return to high level, the device will not be into power down mode. |
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