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59 page 
EDE5108AJBG-1J, EDE5116AJBG-1J Data Sheet E1174E30 (Ver. 3.0) 59 Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clocks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the precharge command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No precharge command should be issued prior to the tWR delay, as DDR2 SDRAM allows the burst interrupt operation only Read by Read or Write by Write at the boundary of burst 4. in3 in1 NOP CK /CK T0 T1 T2 T3 T4 T5 T6 T7 T8 Command DQS, /DQS DQ ≥ tWR Completion of the burst write WL = 3 in0 in2 Posted WRIT PRE Burst Write Followed by Precharge (WL = (RL-1) =3) Posted WRIT CK /CK T0 T1 T2 T3 T4 T5 T6 T7 T9 Command DQS, /DQS DQ WL = 4 in0 in1 in2 in3 PRE ≥ tWR Completion of the burst write NOP Burst Write Followed by Precharge (WL = (RL-1) = 4) |
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