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| EDD51163DBH-6ELS-F |
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 ELPIDA
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37 page 
EDD51163DBH-LS Preliminary Data Sheet E1433E30 (Ver. 3.0) 37 A Write Command to the Consecutive Read Command Interval: To Interrupt the Write Operation Destination row of the consecutive read command Bank address Row address State Operation 1. Same Same ACTIVE DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. 2. Same Different — —* 1 3. Different Any ACTIVE DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. IDLE —* 1 Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address) in0 in1 in2 out0 out1 out3 CK /CK DM DQ Command t1 t0 t2 t3 t4 t5 t6 t7 t8 BL = 4 CL = 3 DQS Data masked READ NOP WRIT High-Z High-Z out2 [WRITE to READ delay = 1 clock cycle] |
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