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Document No. E1433E30 (Ver. 3.0) Date Published October 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2008-2009 PRELIMINARY DATA SHEET 512M bits DDR Mobile RAM WTR (Wide Temperature Range), Low Power Function EDD51163DBH-LS (32M words × 16 bits) Specifications • Density: 512M bits • Organization: 8M words × 16 bits × 4 banks • Package: 60-ball FBGA Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.7V to 1.95V • Data rate: 400Mbps/333Mbps (max.) • 2KB page size Row address: A0 to A12 Column address: A0 to A9 • Four internal banks for concurrent operation • Interface: LVCMOS • Burst lengths (BL): 2, 4, 8, 16 • Burst type (BT): Sequential (2, 4, 8, 16) Interleave (2, 4, 8, 16) • /CAS Latency (CL): 3 • Precharge: auto precharge option for each burst access • Driver strength: normal, 1/2, 1/4, 1/8 • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms Average refresh period: 7.8µs • Operating ambient temperature range TA = −25°C to +85°C Features • DLL is not implemented • Low power consumption • Partial Array Self-Refresh (PASR) • Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor • Deep power-down mode • Double-data-rate architecture; two data transfers per one clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver. • Data inputs, outputs, and DM are synchronized with DQS • DQS is edge-aligned with data for READs; center- aligned with data for WRITEs • Differential clock inputs (CK and /CK) • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Burst termination by burst stop command and precharge command • Wide temperature range TA = −25°C to +85°C |
