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EDD51163DBH-6ELS-F Datasheet(PDF) 8 Page - Elpida Memory |
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EDD51163DBH-6ELS-F Datasheet(HTML) 8 Page - Elpida Memory |
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8 / 60 page  EDD51163DBH-LS Preliminary Data Sheet E1433E30 (Ver. 3.0) 8 AC Characteristics (TA = −25°C to +85°C, VDD and VDDQ = 1.7V to 1.95V, VSS and VSSQ = 0V) -5BLS -6ELS Parameter Symbol min. max. min. max. Unit Notes Clock cycle time tCK 5.0 — 6.0 — ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min. ( tCH, tCL) — min. ( tCH, tCL) — tCK DQ output access time from CK, /CK tAC 2.0 5.0 2.0 5.0 ns 2, 8 DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 tCK DQS output access time from CK, /CK tDQSCK 2.0 5.0 2.0 5.0 ns 2, 8 DQ-out high-impedance time from CK, /CK tHZ — 5.0 — 5.0 ns 5, 8 DQ-out low-impedance time from CK, /CK tLZ 1.0 — 1.0 — ns 6, 8 DQS to DQ skew tDQSQ — 0.4 — 0.5 ns 3 DQ/DQS output hold time from DQS tQH tHP − tQHS — tHP − tQHS — ns 4 Data hold skew factor tQHS — 0.5 — 0.65 ns DQ and DM input setup time tDS 0.48 — 0.6 — ns 3 DQ and DM input hold time tDH 0.48 — 0.6 — ns 3 DQ and DM input pulse width tDIPW 1.6 — 1.6 — ns Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Write preamble setup time tWPRES 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK 7 Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 — 0.2 — tCK DQS falling edge hold time from CK tDSH 0.2 — 0.2 — tCK DQS input high pulse width tDQSH 0.40 — 0.40 — tCK DQS input low pulse width tDQSL 0.40 — 0.40 — tCK Address and control input setup time tIS 0.9 — 1.1 — ns 3 Address and control input hold time tIH 0.9 — 1.1 — ns 3 Address and control input pulse width tIPW 2.3 — 2.7 — ns 3 Mode register set command cycle time tMRD 2 — 2 — tCK Active to Precharge command period tRAS 40 120000 42 120000 ns Active to Active/Auto-refresh command period tRC 55 — 60 — ns Auto-refresh to Active/Auto-refresh command period tRFC 72 — 72 — ns Active to Read/Write delay tRCD 15 — 18 — ns Precharge to active command period tRP 15 — 18 — ns Column address to column address delay tCCD 1 — 1 — tCK Active to active command period tRRD 10 — 12 — ns Write recovery time tWR 15 — 15 — ns |
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