EBE21AE8ACWA datasheet(1/27 Pages) ELPIDA

Part #	EBE21AE8ACWA

Description	2GB Registered DDR2 SDRAM DIMM

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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Document No. E1396E10 (Ver. 1.0)

Date Published October 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2008

DATA SHEET

2GB Registered DDR2 SDRAM DIMM

EBE21AE8ACWA (256M words

× 72 bits, 2 Ranks)

Specifications

• Density: 2GB

• Organization

 256M words × 72 bits, 2 ranks

• Mounting 18 pieces of 1G bits DDR2 SDRAM sealed

in FBGA

• Package: 240-pin socket type dual in line memory

module (DIMM)

 PCB height: 30.0mm

 Lead pitch: 1.0mm

 Lead-free (RoHS compliant)

• Power supply: VDD = 1.8V ± 0.1V

• Data rate: 667Mbps (max.)

• Eight internal banks for concurrent operation

(components)

• Interface: SSTL_18

• Burst lengths (BL): 4, 8

• /CAS Latency (CL): 3, 4, 5

• Precharge: auto precharge option for each burst

access

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

 Average refresh period

7.8

µs at 0°C ≤ TC ≤ +85°C

3.9

µs at +85°C < TC ≤ +95°C

• Operating case temperature range

 TC = 0°C to +95°C

Features

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 2 pieces of register driver

and 1 piece of serial EEPROM (2K bits EEPROM) for

Presence Detect (PD)

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