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TB7101AFT5L1.8F Datasheet(PDF) 7 Page - Toshiba Semiconductor |
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TB7101AFT5L1.8F Datasheet(HTML) 7 Page - Toshiba Semiconductor |
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7 / 22 page  TB7101AF(T5L1.2,F)/(T5L1.5,F)/(T5L1.8,F)/(T5L2.5,F)/(T5L3.3,F) 2008-05-22 7 Electrical Characteristics (unless otherwise specified: Tj = 25°C and VIN = 2.8 to 5.5 V) TB7101AF (T5L1.8, F) Characteristics Symbol Test Condition Min Typ. Max Unit Operating input voltage VIN (OPR) ⎯ 2.8 ⎯ 5.5 V IIN1 VIN = 5 V, VEN = 5 V, VFB = 5 V ⎯ 0.68 0.9 mA Operating current IIN2 VIN = 2.8 V, VEN = 2.8 V, VFB = 2.8 V ⎯ 0.58 0.69 mA Standby current IIN (STBY) VIN = 5 V, VEN = 0 V, VFB = 0 V ⎯ ⎯ 1 μA VIH (EN) 1 VIN = 5 V 1.5 ⎯ ⎯ V VIH (EN) 2 VIN = 2.8 V 1.5 ⎯ ⎯ V VIL (EN) 1 VIN = 5 V ⎯ ⎯ 0.5 V EN threshold voltage VIL (EN) 2 VIN = 2.8 V ⎯ ⎯ 0.5 V IIH (EN) 1 VIN = 5 V, VEN = 5 V 7.6 ⎯ 12.4 μA EN input current IIH (EN) 2 VIN = 2.8 V, VEN = 2.8 V 4.26 ⎯ 6.94 μA VFB1 VIN = 5 V, VEN = 5 V, IOUT = 10 mA 1.746 1.8 1.854 V VFB input voltage VFB2 VIN = 2.8 V, VEN = 2.8 V, IOUT = 10 mA 1.746 1.8 1.854 V High-side switch on-state resistance RDS (ON) (H) VIN = 5 V, VEN = 5 V, ILX = −0.5 A ⎯ 0.27 ⎯ Ω Low-side switch on-state resistance RDS (ON) (L) VIN = 5 V, VEN = 5 V, ILX = 0.5 A ⎯ 0.27 ⎯ Ω High-side switch leakage current ILEAK (H) VIN = 5 V, VEN = 0 V, VLX = 0 V ⎯ ⎯ −1 μA Low-side switch leakage current ILEAK (L) VIN = 5 V, VEN = 0 V, VLX = 5 V ⎯ ⎯ 1 μA fosc1 VIN = 5 V, VEN = 5 V 0.85 1 1.15 MHz Oscillation frequency fosc2 VIN = 2.8 V, VEN = 2.8 V 0.85 1 1.15 MHz tss1 VIN = 5 V, VEN = 5 V, IOUT = 0 A 1 2 ⎯ ms Soft-start time tss2 VIN = 2.8 V, VEN = 2.8 V, IOUT = 0 A 1.4 2.4 ⎯ ms Detection temperature TSD VIN = 5 V ⎯ 160 ⎯ °C Thermal shutdown (TSD) Hysteresis ΔTSD VIN = 5 V ⎯ 20 ⎯ °C Detection votage VUV VIN = VEN 2.2 2.4 2.6 V Recovery voltage VUVR VIN = VEN 2.3 2.5 2.7 V Undervoltage lockout (UVLO) Hysteresis ΔVUV VIN = VEN ⎯ 0.1 ⎯ V LX current limit ILIM VIN = 5 V 1.3 2.8 ⎯ A Note on Electrical Characteristics The test condition Tj = 25°C means a state where any drifts in electrical characteristics incurred by an increase in the chip’s junction temperature can be ignored during pulse testing. |
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