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| 25LC080D-ISLASHMNY |
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7 page 
© 2009 Microchip Technology Inc. DS22151A-page 7 25XX080C/D Block Diagram FIGURE 2-1: READ SEQUENCE SI SO SCK CS HOLD WP STATUS Register I/O Control Memory Control Logic X Dec HV Generator EEPROM Array Page Latches Y Decoder Sense Amp. R/W Control Logic VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS Register WRSR 0000 0001 Write STATUS Register SO SI SCK CS 0 2345 6789 10 11 21 22 23 24 25 26 27 28 29 30 31 1 01 0 0 0 0 01 15 14 13 12 210 76543210 Instruction 16-bit Address Data Out High-Impedance |
