7

Aug. 2009

MITSUBISHI SEMICONDUCTORS <HVIC>

M81721FP

600V HIGH VOLTAGE HALF BRIDGE DRIVER

Note1 : Delay times between input and output signals are not shown in the figure above.

Note2 : The minimum FO pulse width should be more than 500ns (because of FO input filter circuit).

4. FO INPUT TIMING DIAGRAM

When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/

DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again,

the output will respond to the following active input signal.

Note1 : Delay times between input and output signals are not shown in the figure above.

spond to the following active input signals.

HIN

LIN

FO

HOUT

LOUT

HIN

LIN

HOUT

LOUT