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M52S128168A-7BG Datasheet(PDF) 6 Page - Elite Semiconductor Memory Technology Inc.

Part # M52S128168A-7BG
Description  2M x 16 Bit x 4 Banks Synchronous DRAM
Download  47 Pages
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Manufacturer  ESMT [Elite Semiconductor Memory Technology Inc.]
Direct Link  http://www.esmt.com.tw/index.asp
Logo ESMT - Elite Semiconductor Memory Technology Inc.

M52S128168A-7BG Datasheet(HTML) 6 Page - Elite Semiconductor Memory Technology Inc.

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ESMT
M52S128168A
Elite Semiconductor Memory Technology Inc.
Publication Date: Dec. 2008
Revision: 1.2
6/47
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-7
-7.5
-10
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
CAS Latency =3
7
1000
7.5
10
CLK cycle time
CAS Latency =2
tCC
9
9
1000
12
1000
ns
1
CAS Latency =3
5.5
6
7
CLK to valid
output delay
CAS Latency =2
tSAC
7
7
10
ns
1
Output data hold time
tOH
2.5
2.5
2.5
ns
2
CLK high pulse width
tCH
2.5
2.5
3
ns
3
CLK low pulse width
tCL
2.5
2.5
3
ns
3
Input setup time
tSS
2
2
2.5
ns
3
Input hold time
tSH
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CAS Latency =3
5.5
6
7
CLK to output in
Hi-Z
CAS Latency =2
tSHZ
7
7
10
ns
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.


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