ESMT

M52S32162A

Operation Temperature Condition -40°C ~85°C

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2007

Revision : 1.0

23/30

Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page

*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.

2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by

DQM at write interrupted by precharge command is needed to prevent invalid write.

Input data after Row precharge cycle will be masked internally.

3.Burst stop is valid at every burst length.

CL OC K

CK E

AD DR

DQ

DQ M

A1 0 / A P

RA a

CA a

CA b

RA a

DA a 0 DAa 1

DA b 1

DA b 0

DA b 2

Ro w A c t i v e

(A -B a n k )

Wr i t e

(A - B an k )

Bu r s t St o p

Wr i t e

(A - B a n k )

:D o n ' t C a r e

HI G H

DA a 2 DA a 3 DAa 4

DA b 3 DA b 4 DA b 5

P r ec ha rge

(A -B a n k )

*N o t e 2

CS

RA S

CA S

WE

BA

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19