M52L64164A-7BIG datasheet(5/47 Pages) ESMT

Part #	M52L64164A-7BIG

Description	1M x 16 Bit x 4 Banks Synchronous DRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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5 / 47 page

ESMT

M52L64164A

O

peration Temperature Condition -40~85

°C

Elite Semiconductor Memory Technology Inc.

Publication Date: Sep. 2008

Revision: 1.1

5/47

AC OPERATING TEST CONDITIONS (VDD=3.3V

± 0.3V,TA= -40 C

°~ 85 C

°)

Parameter

Value

Unit

Input levels (Vih/Vil)

2.4/0.4

V

Input timing measurement reference level

1.4

V

Input rise and fall time

tr / tf = 1 / 1

ns

Output timing measurement reference level

1.4

V

Output load condition

See Fig.2

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-6

-7

Unit

Note

Row active to row active delay

tRRD(min)

12

14

ns

1

RAS to CAS delay

tRCD(min)

18

20

ns

1

Row precharge time

tRP(min)

18

20

ns

1

tRAS(min)

40

42

ns

1

Row active time

tRAS(max)

100

us

-

@Operating

tRC(min)

58

63

ns

1

Row cycle time

@Auto refresh

tRFC(min)

60

70

ns

1 , 5

Last data in to new col. Address delay

tCDL(min)

1

CLK

2

Last data in to row precharge

tRDL(min)

2

CLK

2

Last data in to burst stop

tBDL(min)

1

CLK

2

Col. Address to col. Address delay

tCCD(min)

1

CLK

3

Mode Register command to Active or Refresh Command

tMRD(min)

2

CLK

-

CAS latency=3

2

Number of valid output data

CAS latency=2

1

ea

4

Refresh period(4,096 rows)

tREF(max)

64

ms

6

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks

5. A new command may be given tRFC after self refresh exit.

6. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posted to any given SDRAM,and

the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is

8x15.6μs.)

Output

870

VOH (DC) =2.4V , IOH = -2 mA

VOL (DC) =0.4V , IOL = 2 mA

Output

50pF

Z0 =50

50pF

50

Vtt = 1.4V

3.3V

1200

Ω

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