ESMT

M52S32162A

Elite Semiconductor Memory Technology Inc.

Publication Date : Dec. 2008

Revision : 1.4

5/30

°

~ 70 C

°)

Parameter

Value

Unit

Input levels (Vih/Vil)

V

Input timing measurement reference level

V

Input rise and fall time

tr / tf = 1 / 1

ns

Output timing measurement reference level

V

Output load condition

See Fig.2

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-6

-7.5

-10

Unit

Note

Row active to row active delay

12

15

20

ns

1

RAS to CAS delay

18

22.5

30

ns

1

Row precharge time

18

22.5

30

ns

1

36

45

50

ns

1

Row active time

100

us

Row cycle time

60

67.5

90

ns

1

Last data in to new col. Address delay

1

CLK

2

Last data in to row precharge

2

CLK

2

Last data in to burst stop

1

CLK

2

Col. Address to col. Address delay

1

CLK

3

Refresh period (4,096 rows)

64

ms

5

CAS latency=3

2

Number of valid output data

CAS latency=2

1

ea

4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.

the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is

8x15.6 μ s.)