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M24L216128DA-70TIG Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc. |
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M24L216128DA-70TIG Datasheet(HTML) 1 Page - Elite Semiconductor Memory Technology Inc. |
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1 / 14 page  ESMT M24L216128DA Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.2 1/14 PSRAM 2-Mbit (128K x 16) Pseudo Static RAM Features ‧ Advanced low-power architecture • High speed: 55 ns, 70 ns • Wide voltage range: 2.7V to 3.6V • Typical active current: 1 mA @ f = 1 MHz • Low standby power • Automatic power-down when deselected Functional Description The M24L216128DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 128K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode, reducing power consumption dramatically when deselected ( 1 CE HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins(I/O0 through I/O15) are placed in a high-impedance state when the chip is deselected ( 1 CE HIGH, CE2 LOW) or OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables ( 1 CE LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. Seethe Truth Table for a complete description of read and write modes. Logic Block Diagram |
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