ESMT

M24L216128DA

Elite Semiconductor Memory Technology Inc.

Publication Date : Jul. 2008

Revision : 1.2

5/14

AC Test Loads and Waveforms

Parameters

Unit

R1

22000

Ω

R2

22000

Ω

11000

Ω

1.50

V

Switching Characteristics Over the Operating Range[10]

-55 [14]

-70

Parameter

Description

Min.

Max.

Min.

Max.

Unit

Read Cycle

Read Cycle Time

55[14]

70

ns

Address to Data Valid

55

70

ns

Data Hold from Address Change

5

10

ns

1

CE LOW and CE2 HIGH to Data Valid

55

70

ns

OE LOW to Data Valid

25

35

ns

OE LOW to LOW Z[11, 12]

5

5

ns

OE HIGH to High Z[11, 12]

25

25

ns

1

CE LOW and CE2 HIGH to Low Z[11, 12]

2

5

ns

1

CE HIGH and CE2 LOW to High Z[11, 12]

25

25

ns

BLE

/ BHE LOW to Data Valid

55

70

ns

BLE

/ BHE LOW to Low Z[11, 12]

5

5

ns

BLE

/ BHE HIGH to High Z[11, 12]

10

25

ns

Address Skew

0

10

ns

Write Cycle[12]

Write Cycle Time

55

70

ns

1

CE LOW and CE2 HIGH to Write End

45

55

ns

Address Set-Up to Write End

45

55

ns

Address Hold from Write End

0

0

ns

Address Set-Up to Write Start

0

0

ns

Notes:

12. High-Z and Low-Z parameters are characterized and are not 100% tested.

13. The internal write time of the memory is defined by the overlap of WE ,

1

All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data

input set-up and hold timing should be referenced to the edge of the signal that terminates write.

be stable within 10 ns after the start of the read cycle.