M13S2561616A datasheet(7/49 Pages) ESMT

Part #	M13S2561616A

Description	4M x 16 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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7 / 49 page

ESMT

M13S2561616A

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2009

Revision : 2.0

7/49

AC Timing Parameter & Specifications-continued

-4

-5

-6

Parameter

Symbol

min

max

min

max

min

max

Unit

Half Clock Period

tHP

tCLmin or

tCHmin

-

tCLmin or

tCHmin

-

tCLmin or

tCHmin

-

ns

DQ-DQS output hold time

tQH

tHP-tQHS

-

tHP-tQHS

-

tHP-tQHS

-

ns

Data hold skew factor

tQHS

-

0.45

-

0.45

-

0.5

ns

ACTIVE to PRECHARGE command

tRAS

40

70K

40

70K

42

70K

ns

Row Cycle Time

tRC

52

-

55

-

60

-

ns

AUTO REFRESH Row Cycle Time

tRFC

64

-

70

-

72

-

ns

ACTIVE to READ,WRITE delay

tRCD

15

-

15

-

18

-

ns

PRECHARGE command period

tRP

15

-

15

-

18

-

ns

ACTIVE to READ with AUTOPRECHARGE

command

tRAP

18

120K

18

120K

18

120K

ns

ACTIVE bank A to ACTIVE bank B

command

tRRD

8

-

10

-

12

-

ns

Write recovery time

tWR

15

-

15

-

15

-

ns

Write data in to READ command delay

tWTR

2

-

2

-

1

-

tCK

Col. Address to Col. Address delay

tCCD

1

-

1

-

1

-

tCK

Average periodic refresh interval

tREFI

-

7.8

-

7.8

-

7.8

us

Write preamble

tWPRE

0.25

-

0.25

-

0.25

-

tCK

Write postamble

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS read preamble

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

DQS read postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Clock to DQS write preamble setup time

tWPRES

0

-

0

-

0

-

ns

Load Mode Register / Extended Mode

register cycle time

tMRD

2

-

2

-

1

-

tCK

Exit self refresh to READ command

tXSRD

200

-

200

-

200

-

tCK

Exit self refresh to non-READ command

tXSNR

75

-

75

-

75

-

ns

Autoprecharge write recovery + Precharge

time

tDAL

30

-

30

-

30

ns

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