M13S2561616A-6BG datasheet(5/49 Pages) ESMT

Part #	M13S2561616A-6BG

Description	4M x 16 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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5 / 49 page

ESMT

M13S2561616A

Elite Semiconductor Memory Technology Inc.

Publication Date : Sep. 2009

Revision : 2.0

5/49

DC Specifications

Version

Parameter

Symbol

Test Condition

-4

-5

-6

Unit Note

Operation Current

(One Bank Active)

IDD0

tRC = tRC (min), tCK = tCK (min)

Active – Precharge

140

130

120

mA

Operation Current

(One Bank Active)

IDD1

Burst Length = 2, tRC = tRC (min), CL= 2.5,

IOUT = 0mA,

Active-Read- Precharge

190

185

165

mA

Precharge Power-down

Standby Current

IDD2P

CKE

≤ V

IL(max), tCK = tCK (min), All banks idle

40

30

25

mA

Idle Standby Current

IDD2N

CKE

≥ V

IH(min),

CS

≥ V

IH(min), tCK = tCK (min)

70

60

55

mA

Active Power-down

Standby Current

IDD3P

All banks ACT, CKE

≤ V

IL(max), tCK = tCK (min)

55

50

45

mA

Active Standby Current

IDD3N

One bank; Active-Precharge, tRC = tRAS(max),

tCK = tCK (min)

120

95

90

mA

Operation Current (Read)

IDD4R

Burst Length = 2, CL= 2.5 , tCK = tCK (min),

IOUT = 0mA

300

290

250

mA

Operation Current (Write)

IDD4W

Burst Length = 2, CL= 2.5 , tCK = tCK (min)

300

290

250

mA

Auto Refresh Current

IDD5

tRC ≥ tRFC(min)

300

270

250

mA

Self Refresh Current

IDD6

CKE

≤ 0.2V

6

5

mA

1

Operation Current

(Four Bank Operation)

IDD7

Four bank interleaving with BL = 4, tRC = tRC(min),

burst mode; Read with auto precharge;

Address and control input on NOP edge are not

changing. IOUT = 0mA

350

300

270

mA

Note: 1. Enable on-chip refresh and address counters.

AC Operation Conditions & Timing Specification

AC Operation Conditions

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

VIH(AC)

VREF + 0.31

V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

VIL(AC)

VREF - 0.31

V

Input Different Voltage, CLK and CLK inputs

VID(AC)

0.7

VDDQ+0.6

V

1

Input Crossing Point Voltage, CLK and CLK inputs

VIX(AC)

0.5*VDDQ-0.2

0.5*VDDQ+0.2

V

2

Note: 1. VID is the magnitude of the difference between the input level on CLK and the input on CLK .

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the

same.

Input / Output Capacitance

(VDD = 2.3V~2.7V, VDDQ =2.3V~2.7V, TA = 25 C

° , f = 1MHz)

(VDD = 2.4V~2.8V, VDDQ = 2.4V~2.8V, TA = 25 C

° , f = 1MHz (only for speed -4))

Parameter

Symbol

Min

Max

Unit

Input capacitance

(A0~A12, BA0~BA1, CKE, CS , RAS , CAS , WE )

CIN1

2.0

3.0

pF

Input capacitance (CLK, CLK )

CIN2

2.0

3.0

pF

Data & DQS input/output capacitance

COUT

4.0

5.0

pF

Input capacitance (DM)

CIN3

4.0

5.0

pF

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