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M13S128168A-4BG Datasheet(PDF) 11 Page - Elite Semiconductor Memory Technology Inc. |
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M13S128168A-4BG Datasheet(HTML) 11 Page - Elite Semiconductor Memory Technology Inc. |
11 / 49 page ESMT M13S128168A Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2008 Revision : 2.2 11/49 Burst Address Ordering for Burst Length Burst Length Starting Address (A2, A1,A0) Sequential Mode Interleave Mode xx0 0, 1 0, 1 2 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 4 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enable automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. M13S128168A also support a weak drive strength option, intended for lighter load and/or point-to-point environments. Mode Register Set *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. 0 1 23 4 5 678 CO MM A N D t CK Pre c h a rg e Al l B a n k s Mo d e R egi s t e r S e t An y C o mma n d t RP *2 *1 CL K CL K |
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