M13S64164A-6TG datasheet(6/48 Pages) ESMT

Part #	M13S64164A-6TG

Description	1M x 16 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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6 / 48 page

ESMT

M13S64164A

Elite Semiconductor Memory Technology Inc.

Publication Date : Jun. 2009

Revision : 1.4

6/48

AC Operating Test Conditions

Parameter

Value

Unit

Input reference voltage for clock (VREF)

0.5*VDDQ

V

Input signal maximum peak swing

1.5

V

Input signal minimum slew rate

1.0

V/ns

Input levels (VIH/VIL)

VREF+0.31/VREF-0.31

V

Input timing measurement reference level

VREF

V

Output timing reference level

VTT

V

AC Timing Parameter & Specifications

(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA =0 C

°

to 70 C

°)

-5

-6

Parameter

Symbol

min

max

min

max

Unit

CL2

7.5

12

7.5

12

CL2.5

6.0

12

6.0

12

Clock Period

CL3

tCK

5.0

8

6.0

10

ns

Access time from CLK/ CLK

tAC

-0.7

+0.7

-0.7

+0.7

ns

CLK high-level width

tCH

0.45

0.55

0.45

0.55

tCK

CLK low-level width

tCL

0.45

0.55

0.45

0.55

tCK

Data strobe edge to clock edge

tDQSCK

-0.6

+0.6

-0.6

+0.6

ns

Clock to first rising edge of DQS delay

tDQSS

0.75

1.25

0.75

1.25

tCK

Data-in and DM setup time (to DQS)

tDS

0.45

-

0.45

-

ns

Data-in and DM hold time (to DQS)

tDH

0.45

-

0.45

-

ns

DQ and DM input pulse width (for each input)

tDIPW

1.75

-

1.75

-

ns

Input setup time (fast slew rate)

tIS

0.75

-

0.75

-

ns

Input hold time (fast slew rate)

tIH

0.75

-

0.75

-

ns

Input setup time (slow slew rate)

tIS

0.8

-

0.8

-

ns

Input hold time (slow slew rate)

tIH

0.8

-

0.8

-

ns

Control and Address input pulse width

tIPW

2.2

-

2.2

-

ns

DQS input high pulse width

tDQSH

0.4

0.6

0.4

0.6

tCK

DQS input low pulse width

tDQSL

0.4

0.6

0.4

0.6

tCK

DQS falling edge to CLK rising-setup time

tDSS

0.2

-

0.2

-

tCK

DQS falling edge from CLK rising-hold time

tDSH

0.2

-

0.2

-

tCK

Data strobe edge to output data edge

tDQSQ

-

0.45

-

0.45

ns

Data-out high-impedance window from

CLK/ CLK

tHZ

-0.7

+0.7

-0.7

+0.7

ns

Data-out low-impedance window from

CLK/ CLK

tLZ

-0.7

+0.7

-0.7

+0.7

ns

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