M12S128168A-7TG datasheet(8/45 Pages) ESMT

Part #	M12S128168A-7TG

Description	2M x 16 Bit x 4 Banks Synchronous DRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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8 / 45 page

ESMT

M12S128168A

Elite Semiconductor Memory Technology Inc.

Publication Date: Apr. 2008

Revision: 1.1

8/45

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1 CKEn CS RAS CAS WE DQM

BA0

BA1

A10/AP

A11

A9~A0

Note

Mode Register set

H

X

L

X

OP CODE

1,2

Register

Extended Mode Register

Set

H

X

L

X

OP CODE

1,2

Auto Refresh

H

3

Entry

H

L

H

X

3

L

H

X

3

Refresh

Self

Refresh

Exit

L

H

X

3

Bank Active & Row Addr.

H

X

L

H

X

V

Row Address

Auto Precharge Disable

L

4

Read &

Column Address

Auto Precharge Enable

H

X

L

H

L

H

X

V

H

Column

Address

(A0~A8)

4,5

Auto Precharge Disable

L

4

Write &

Column Address

Auto Precharge Enable

H

X

L

H

L

X

V

H

Column

Address

(A0~A8)

4,5

Burst Stop

H

X

L

H

L

X

6

Bank Selection

V

L

Precharge

All Banks

H

X

L

H

L

X

H

X

H

X

Entry

H

L

V

X

Clock Suspend or

Active Power Down

Exit

L

H

X

H

X

Entry

H

L

H

X

H

X

Precharge Power Down Mode

Exit

L

H

L

V

X

DQM

H

X

V

X

7

No Operating Command

H

X

H

X

Entry

H

L

H

L

X

Deep Power Down Mode

Exit

L

H

X

(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )

Note :

1.OP Code : Operating Code

A0~A11 & BA0~BA1 : Program keys. (@ MRS)

2.MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge of command is meant by “Auto”.

Auto/self refresh can be issued only at all banks idle state.

4.BA0~BA1 : Bank select addresses.

If BA0 and BA1 are “Low” at read ,write , row active and precharge ,bank A is selected.

If BA0 is “Low” and BA1 is “High” at read ,write , row active and precharge ,bank B is selected.

If BA0 is “High” and BA1 is “Low” at read ,write , row active and precharge ,bank C is selected.

If BA0 and BA1 are “High” at read ,write , row active and precharge ,bank D is selected

If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.

5.During burst read or write with auto precharge. new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but

makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

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