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MA009AD Datasheet(PDF) 8 Page - Megawin Technology Co., Ltd |
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MA009AD Datasheet(HTML) 8 Page - Megawin Technology Co., Ltd |
8 / 19 page 8 MA009A Technical Summary MEGAWIN Command Definition Instruction OPCODE Operand1 Data Comments C_RES FEFFH Software chip reset, all register value will be reset to 0 (default value). C_EVTCLR 13H Clear all event, P0EVT and P1EVT will be cleared. W_ADDR FDH 8-bit data Write chip address, must match the pin status of A2 ~A0 to enable MA009. Input port P0 W_P0PR 04H 8-bit data Write P0PR (pull high control register) W_P0PSR 0AH 8-bit data Write P0PSR (strong pull high selection register) W_P0IEN 10H 8-bit data Write P0IEN (interrupts enable register) R_P0 3DH 8-bit data (R) Read P0 R_P0PR 34H 8-bit data (R) Read P0PR R_P0PSR 3AH 8-bit data (R) Read P0PSR R_P0EVT 43H 8-bit data (R) Read P0EVT (interrupts events status register) I/O port P1 W_P1 0EH 8-bit data Write P1 W_P1CR 02H 8-bit data Write P1CR (I/O control register) W_P1POR 05H 8-bit data Write P1POR (pull high/output mode control register) W_P1PSR 0BH 8-bit data Write P1PSR W_P1SCR 08H 8-bit data Write P1SCR (sink control register) W_P1IEN 11H 8-bit data Write P1IEN R_P1 3EH 8-bit data (R) Read P1 R_P1CR 32H 8-bit data (R) Read P1CR R_P1POR 35H 8-bit data (R) Read P1POR R_P1PSR 3BH 8-bit data (R) Read P1PSR R_P1SCR 38H 8-bit data (R) Read P1SCR R_P1EVT 44H 8-bit data (R) Read P1EVT Output port P2 W_P2 0FH 8-bit data Write P2 W_P2OR 06H 8-bit data Write P2OR (output mode control register) W_P2SCR 09H 8-bit data Write P2SCR W_P2PR 0CH 8-bit data Write P2PR R_P2OR 36H 8-bit data (R) Read P2OR R_P2SCR 39H 8-bit data (R) Read P2SCR R_P2PR 3CH 8-bit data (R) Read P2PR The command should be sent from MSB to LSB, and the signal must be stable in clock rising edge. |
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