Typical Characteristics - Phase Noise

Reliability

VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow

simulation. The VX-700 family is capable of meeting the following qualification tests:

Table 3. Environmental Compliance

Parameter

Conditions

Mechanical Shock

MIL-STD-883, Method 2002

Mechanical Vibration

MIL-STD-883, Method 2007

Solderability

MIL-STD-883, Method 2003

Gross and Fine Leak

MIL-STD-883, Method 1014

Resistance to Solvents

MIL-STD-883, Method 2015

Moisture Sensitivity Level

MSL 1

Contact Pads

Gold over Nickel

Table 4. Absolute Maximum Ratings

Parameter

Symbol

Ratings

Unit

Power Supply

V

DD

0 to 6

V

Output Current

I

OUT

25

mA

Voltage Control Range

V

C

0 to V

CC

V

Storage Temperature

TS

-55 to 125

°C

Soldering Temp/Time

T

LS

260 / 40

°C / sec

Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not

implied at these or any other conditions in excess of conditions represented in the operational sections of this datasheet.

Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is

also possible if OD or Vc is applied before Vcc.

Although ESD protection circuitry has been designed into the VX-700 proper precautions should be taken when handling

and mounting. VI employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing

and design protection evaluation.

Table 5. ESD Ratings

Model

Minimum

Conditions

Human Body Model

500V

MIL-STD-883, Method 3015

Charged Device Model

500V

JESD22-C101

Suggested Output Load Configurations

Page4

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Figure 3 Standard PECL Output Configuration

Figure 4 Single Resistor Termination Scheme

Resistor values are typically 120 to 240 ohms

Figure 5 Pull-Up Pull-Down Termination

The VX-700 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 3. There are numerous application notes

on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, and a pull-up/pull-down scheme

as shown in Figure 5. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.

One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-

nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching

into account. Load matching and power supply noise are the main contributors to jitter related problems.