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Page 5 of 9

Table 7. Pin Functions

Pin #

Symbol

I/O

Level

Function

1

SEL0

I

LVCMOS

2

SEL1

I

LVCMOS

3

GND

GND

Supply

Case and Electrical Ground

4

Not present

5

VMON

O

VCXO Control Voltage Monitor

Under locked conditions VMON should be > 0.3V and <3.0V. The input frequency may

be out of range if the voltage exceeds these levels

6

OD

I

LVCMOS

Output Disable

Disabled = Logic “1”

Enabled = Logic “0” or no connect

7

GND

GND

Supply

Case and Electrical Ground

8

FOUT

O

LCPECL. LVDS or

LVCMOS

Frequency Output

9

CFOUT

O

LVPECL, LVDS or

LVCMOS

Complementary Frequency Output – Note for LVCMOS option this pad will be tied to

GND.

10

LD

O

LVCMOS

Lock Detect

Locked = Logic “1”

Loss of Signal = Logic “0”

11

GND

GND

Supply

Case and Electrical Ground

12

GND

GND

Supply

Case and Electrical Ground

13

FIN

I

LVCMOS or

LVPECL

Input Frequency – AC Coupled

14

VCC

VCC

Supply

Power Supply Voltage (3.3 V ±5%)

vided in a Specification Control Drawing. For single input configurations it is recommended that SEL0 and SEL1 are tied to ground.

Pin Configuration

Rev: 01Apr2009

Table 8. Control Logic (LVCMOS)

SEL0

SEL1

Reference Clock Input

00

F

1

01

F

2

10

F

3

11

F

4

Figure 6. Pin Configuration